Nano-CMOS Gate Dielectric Engineering

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The text also addresses the essence of thin film deposition, etching, and process integration of high-k materials in an actual CMOS process. Fascinating in both content and approach, Nano-CMOS Gate Dielectric Engineering explains all of the necessary physics in a highly readable manner and supplements this with numerous intuitive illustrations and tables.

Covering almost every aspect of high-k gate dielectric engineering for nano-CMOS technology, this is a perfect reference book for graduate students needing a better understanding of developing technology as well as researchers and engineers needing to get ahead in microelectronic engineering and materials science.

Though it involves quite a lot of physics, it is never less than fascinating, through its many intuitive illustrations and tables. Routledge eBooks are available through VitalSource. An eBook version of this title already exists in your shopping cart. However, this layer has much smaller k values and becomes the lower bound of the thinnest EOT, and needs to be minimized for the subnanometer EOT dielectric. The different depths were obtained by argon sputtering for 2. This treatment should be able to minimize the artifacts due to ion knock-on effects. : Nano-CMOS Gate Dielectric Engineering () : Hei Wong : Books

With Gaussian decomposition, three oxygen bonding states, i. It indicates that the thermal annealing does not only lead to the formation of the interfacial silicate layer, but also results in the Si substrate oxidation. With capacitance-voltage measurements, the k value of this layer is estimated to be in the range of 8 to Thus, from the EOT point of view, this layer contributes over 0. In addition, the interface roughness was significantly increased which led to further channel mobility degradation.

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Hence, although some of the device properties may be improved by forming the interfacial silicate layer and SiO 2 layer, the silicate or SiO 2 layer has much smaller k value and becomes the lower bound of the thinnest EOT. It needs to be minimized for the subnanometer EOT dielectric.

The rough interface should be due to the oxidation of tungsten and the reaction between La 2 O 3 and tungsten at the interface. Unlike silicon oxide or silicon nitride, high- k metal oxides are less thermally stable and are easier to be crystallized [ 1 , 18 ].

1st Edition

At even higher temperatures, serious crystallization, partial decomposition of metal-oxygen bonds, and phase separation of silicate will occur [ 1 , 2 ]. Thus, the process sequence of a high- k -based process has to be adjusted so as to avoid the as-deposited high- k material from being exposed at a high-temperature ambient. In addition, to avoid the knock-on of metal atoms into the substrate, the high- k film should not be deposited before the ion implantation unless a very thick protection layer is introduced.

The gate-first process is similar to the conventional one. It requires both the high- k and the gate electrode material to be stable at the annealing temperature.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

The high-temperature process also led to the non-uniformity of the film thickness. In the gate-last process, the high- k dielectric was deposited and then an intermediate poly-Si layer was deposited and patterned. This process avoids the possible knock-on of the high- k metal into the substrate and minimizes the number of high-temperature cycles on the gate material.

However, this process still causes the high- k layer to be exposed to high temperatures. This process reduces the interfacial low- k layer growth and seems to be a viable option for preparing the ultimate EOT dielectric film although there are some disadvantages associated with this process sequence re-shuttling. This process sequence is for avoiding high-temperature cycles on the as-deposited high- k film so as to suppress the growth of the interface silicate layer. In future technology nodes, the gate dielectric thickness of the CMOS devices will be scaled down to the subnanometer range.

Lanthanum-based dielectric films have been considered to be suitable candidates for this application. These interface layers will become the critical constraint for the smallest achievable EOT, and they would also cause a number of instability issues and induce device performance degradation. These issues can be minimized by lowering the thermal budgets and re-shuttling the process sequences. HW generated the research idea, analyzed the data, and wrote the paper. JeZ performed the XPS analysis. KK and HI provided the samples. HW has given final approval of the version to be published.

All authors read and approved the final manuscript. National Center for Biotechnology Information , U. Journal List Nanoscale Res Lett v.

  1. On the scaling of lanthanum oxide gate dielectric film into the subnanometer EOT range.
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  6. Nanoscale Res Lett. Published online Sep 5.

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    Nano-CMOS Gate Dielectric Engineering Nano-CMOS Gate Dielectric Engineering
    Nano-CMOS Gate Dielectric Engineering Nano-CMOS Gate Dielectric Engineering
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    Nano-CMOS Gate Dielectric Engineering Nano-CMOS Gate Dielectric Engineering

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